sigma = q (n mu_n + p mu_p)
Conductivity equals charge times the sum of electron density times electron mobility and hole density times hole mobility.
Conductivity from electron and hole densities and mobilities.
- sigma
- conductivity (S/m)
- q
- elementary charge (C)
- n
- electron concentration (1/m^3)
- p
- hole concentration (1/m^3)
- mu_n
- electron mobility (m^2/(V s))
- mu_p
- hole mobility (m^2/(V s))
Use when — Standard drift model with defined carrier populations.
Common trap — Calling n-type material negatively charged overall.
n = p = n_i
Electron concentration equals hole concentration equals the intrinsic carrier concentration.
Equal electron and hole concentrations in an intrinsic semiconductor.
- n
- electron concentration (1/m^3)
- p
- hole concentration (1/m^3)
- n_i
- intrinsic carrier concentration (1/m^3)
Use when — Thermal equilibrium in intrinsic material only.
Common trap — Applying this equality to doped material.
Forward bias: p-side at higher potential than n-side
A junction is forward biased when the p-side terminal is at a higher potential than the n-side terminal.
Bias direction from terminal potentials in the conventional junction orientation.
Use when — Device orientation is clearly shown in the circuit.
Common trap — Deciding bias direction from the symbol shape alone without checking circuit potentials.
Ideal conducting diode acts as a short circuit in forward conduction
An ideal forward-conducting diode is modelled as a short circuit.
Short-circuit approximation used only when the ideal model is explicitly or conventionally adopted.
Use when — Only when the question explicitly or conventionally adopts the ideal model.
Common trap — Using the ideal-switch model for a measured current-voltage curve.
V_out is approximately equal to V_Z
Output voltage is approximately equal to the Zener breakdown voltage under proper regulation.
Regulated output stays near the breakdown voltage.
- V_out
- regulated output voltage (V)
- V_Z
- Zener breakdown voltage (V)
Use when — Reverse breakdown with series current limiting, and the device stays within regulation and rating limits.
Common trap — Omitting the series resistor or the load current from the analysis.
Y = A AND B; Y = A OR B; Y = NOT A
Output Y equals A AND B, or A OR B, or NOT A, depending on the gate.
AND, OR and NOT Boolean relations.
- A
- logic input (binary)
- B
- logic input (binary)
- Y
- logic output (binary)
Use when — Positive-logic convention.
Common trap — Treating ordinary arithmetic addition as Boolean OR without context.
NAND = NOT (A AND B); NOR = NOT (A OR B)
NAND equals NOT of A AND B; NOR equals NOT of A OR B.
Complemented gates built from AND or OR followed by NOT.
- A
- logic input (binary)
- B
- logic input (binary)
Use when — Positive-logic convention.
Common trap — Complementing the inputs instead of complementing the gate output.